At present, silicon sensors on the wafer level are tested purely electrically. In practice, to do this, test and handling systems that generate electric stimuli by placing needles at specific contact points of the sensor elements are used to detect voltages and currents at different temperatures and thus to evaluate the electric function parameters of the individual sensor elements. The moving and fine positioning of the needles at the contact points must be performed separately for each sensor element on the wafer. The more sensor elements disposed on the wafer, the more time accordingly required for the mechanical positioning of the contact needles. Furthermore, this positioning is becoming ever more critical since the sensor elements are becoming smaller and smaller.
The individual sensor elements are measured and adjusted during the application of non-electric stimuli such as pressure, acceleration, rate of rotation, etc., only after separation and packaging or installation.
DE 696 33 713 T2 describes measures for electronically selecting and electronically testing chips that are not separated on a wafer. Thus, bad chips are to be identified and eliminated even before the separation in order to continue the manufacturing process using only the chips that are good at the time of testing and in this manner to achieve a highest possible yield of functional components. To this end, all chips that are implemented on a wafer are connected to a bus system having a bus line for wafer supply voltage and a bus line for wafer grounding. Electric energy is supplied to the chips via this bus system. Defects, in particular short-circuited chips, are able to be identified and, where necessary, separated from the bus system. Furthermore, DE 696 33 713 T2 suggests that the integrated circuits of the individual chips be designed such that they may be optionally operated actively or in a bypass mode as part of the test carried out in the wafer composite. If a chip is actively connected, electric test signals are applied to its contact points via the bus system and via the neighboring chips existing in the bypass mode in order to check the functionality of the selected chip.